Hi Tero,
On Thursday 19 June 2014 04:42 PM, Tero Kristo wrote:
> On 05/29/2014 09:38 AM, Kishon Vijay Abraham I wrote:
>> From: Keerthy <j-keerthy@xxxxxx>
>>
>> Change the parent of apll_pcie_in_clk_mux to dpll_pcie_ref_m2ldo_ck
>> from dpll_pcie_ref_ck.
>
> Why? Needs a better changelog also.
Figure 26-22. DPLL_PCIE_REF Functional Block Diagram in vE of DRA7xx ES1.0 TRM
shows the signal name for the output of post divider (M2) is CLKOUTLDO.
Figure 26-21. PCIe PHY Clock Generator Overview shows CLKOUTLDO is used as
input to apll mux.
So the actual output of dpll should be dpll_pcie_ref_m2ldo_ck instead of
dpll_pcie_ref_ck (which is the input of apll mux).
Thanks
Kishon
>
> -Tero
>
>>
>> Cc: Rajendra Nayak <rnayak@xxxxxx>
>> Cc: Tero Kristo <t-kristo@xxxxxx>
>> Cc: Paul Walmsley <paul@xxxxxxxxx>
>> Signed-off-by: Keerthy <j-keerthy@xxxxxx>
>> Signed-off-by: Kishon Vijay Abraham I <kishon@xxxxxx>
>> ---
>> arch/arm/boot/dts/dra7xx-clocks.dtsi | 2 +-
>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi
>> b/arch/arm/boot/dts/dra7xx-clocks.dtsi
>> index 55e95c5..44993ec 100644
>> --- a/arch/arm/boot/dts/dra7xx-clocks.dtsi
>> +++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi
>> @@ -1152,7 +1152,7 @@
>>
>> apll_pcie_in_clk_mux: apll_pcie_in_clk_mux@4ae06118 {
>> compatible = "ti,mux-clock";
>> - clocks = <&dpll_pcie_ref_ck>, <&pciesref_acs_clk_ck>;
>> + clocks = <&dpll_pcie_ref_m2ldo_ck>, <&pciesref_acs_clk_ck>;
>> #clock-cells = <0>;
>> reg = <0x021c 0x4>;
>> ti,bit-shift = <7>;
>>
>
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