Re: [PATCH v2 07/18] ARM: dts: DRA7: Change the parent of apll_pcie_in_clk_mux to dpll_pcie_ref_m2ldo_ck

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On 05/29/2014 09:38 AM, Kishon Vijay Abraham I wrote:
From: Keerthy <j-keerthy@xxxxxx>

Change the parent of apll_pcie_in_clk_mux to dpll_pcie_ref_m2ldo_ck
from dpll_pcie_ref_ck.

Why? Needs a better changelog also.

-Tero


Cc: Rajendra Nayak <rnayak@xxxxxx>
Cc: Tero Kristo <t-kristo@xxxxxx>
Cc: Paul Walmsley <paul@xxxxxxxxx>
Signed-off-by: Keerthy <j-keerthy@xxxxxx>
Signed-off-by: Kishon Vijay Abraham I <kishon@xxxxxx>
---
  arch/arm/boot/dts/dra7xx-clocks.dtsi |    2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/dra7xx-clocks.dtsi
index 55e95c5..44993ec 100644
--- a/arch/arm/boot/dts/dra7xx-clocks.dtsi
+++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi
@@ -1152,7 +1152,7 @@

  	apll_pcie_in_clk_mux: apll_pcie_in_clk_mux@4ae06118 {
  		compatible = "ti,mux-clock";
-		clocks = <&dpll_pcie_ref_ck>, <&pciesref_acs_clk_ck>;
+		clocks = <&dpll_pcie_ref_m2ldo_ck>, <&pciesref_acs_clk_ck>;
  		#clock-cells = <0>;
  		reg = <0x021c 0x4>;
  		ti,bit-shift = <7>;


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