Hi Babu, On 9/23/24 1:21 PM, Moger, Babu wrote: > Hi Reinette, > > On 9/19/24 12:08, Reinette Chatre wrote: >> Hi Babu, >> >> On 9/4/24 3:21 PM, Babu Moger wrote: >>> +/* >>> + * ABMC counters can be configured by writing to L3_QOS_ABMC_CFG. >>> + * @bw_type : Bandwidth configuration(supported by BMEC) >>> + * tracked by the @cntr_id. >>> + * @bw_src : Bandwidth source (RMID or CLOSID). >>> + * @reserved1 : Reserved. >>> + * @is_clos : @bw_src field is a CLOSID (not an RMID). >>> + * @cntr_id : Counter identifier. >>> + * @reserved : Reserved. >>> + * @cntr_en : Tracking enable bit. >>> + * @cfg_en : Configuration enable bit. >>> + * >>> + * Configuration and tracking: >>> + * CfgEn=1,CtrEn=0 : Configure CtrID and but no tracking the events yet. >>> + * CfgEn=1,CtrEn=1 : Configure CtrID and start tracking events. >> >> Thanks for moving the text ... could it now be made to match the new (outside >> AMD arch document) destination? For example, "CfgEn" becomes "@cfg_en", > > Sure. Will do. > >> "CtrID" becomes "@cntr_id" etc. Also please fix language, for example >> what does "and but no tracking the events yet" mean? So far this work >> has focused on "counting" vs "not counting" events and it is not > > I will change the text to "not counting". Hope this will clarify here. > >> clear how this "tracking" fits it ... this seems to be the hardware >> view that means "tracking the RMID to which @cntr_id is assigned"? >> Please help readers to understand how the implementation is supported >> by the hardware. > > I have checked with hw team on this. > CfgEn: This corresponds counter assignment. To be specific this corresponds to *hardware* counter assignment? This is because software sets CfgEn to 1 whether it is assigned from kernel perspective or not. Actually ... when I look at the AMD spec it becomes more clear to me. If I understand the spec correctly the CfgEn bit is used to coordinate changes between OS and HW. Seems like OS can leisurely write to any fields of L3_QOS_ABMC_CFG, but only when CfgEn bit is set will the actual hardware configuration be performed. > CtrEn: This is to start or stop counting. > We always set this to 1 to start counting. Understood. Now that I read this portion of AMD spec it is more clear to me and I understand why CfgEn is set in both counter assign and unassign. Reinette
