Hi Reinette,
On 5/7/2024 6:06 PM, Reinette Chatre wrote:
Hi Babu,
On 5/7/2024 1:40 PM, Moger, Babu wrote:
On 5/3/24 18:32, Reinette Chatre wrote:
On 3/28/2024 6:06 PM, Babu Moger wrote:
ABMC (Bandwidth Monitoring Event Configuration) counters can be configured
by writing to L3_QOS_ABMC_CFG MSR. When ABMC is enabled, the user can
configure a counter by writing to L3_QOS_ABMC_CFG setting the CfgEn field
while specifying the Bandwidth Source, Bandwidth Types, and Counter
Identifier. Add the MSR definition and individual field definitions.
MSR L3_QOS_ABMC_CFG (C000_03FDh) definitions.
==========================================================================
Bits Mnemonic Description Access Type Reset Value
==========================================================================
63 CfgEn Configuration Enable R/W 0
62 CtrEn Counter Enable R/W 0
61:53 – Reserved MBZ 0
52:48 CtrID Counter Identifier R/W 0
47 IsCOS BwSrc field is a COS R/W 0
(not an RMID)
46:44 – Reserved MBZ 0
43:32 BwSrc Bandwidth Source R/W 0
(RMID or COS)
31:0 BwType Bandwidth types to R/W 0
track for this counter
==========================================================================
The feature details are documentd in the APM listed below [1].
documentd -> documented
Sure.
[1] AMD64 Architecture Programmer's Manual Volume 2: System Programming
Publication # 24593 Revision 3.41 section 19.3.3.3 Assignable Bandwidth
Monitoring (ABMC).
This changelog is purely a summary of the hardware architecture. I have not come
across a clear explanation on how this architecture is intended to be supported
by resctrl. When would resctrl need/want to set particular fields? What is
the mapping to resctrl?
Something like this in the changelog?
ABMC feature provides an option to assign(or pin) an RMID to the
hardware counter and monitor the bandwidth for a longer duration.
Regarding "a longer duration":
https://lore.kernel.org/lkml/b5e68d85-4bf2-4e55-a9c1-b39cb7d94db6@xxxxxxxxx/
Sure. Will take care of this.
Hardware counters can be configured by writing to L3_QOS_ABMC_CFG MSR.
Configuration is done by setting the CfgEn field while specifying the
Bandwidth Source(RMID or CLOS), Bandwidth Types, and Counter Identifier.
Add the configuration register definition.
This still looks to me like a cryptic description of the hardware architecture.
Could you please spell out to me how the above answers each of my questions?
Will try to elaborate this in next revision.
Thanks
- Babu Moger
