Hi, On 11/28/23 06:20, Borislav Petkov wrote: > On Thu, Nov 02, 2023 at 11:42:22AM +0000, Muralidhara M K wrote: >> From: Muralidhara M K <muralidhara.mk@xxxxxxx> >> >> AMD systems with Scalable MCA, each machine check error of a SMCA bank >> type has an associated bit position in the bank's control (CTL) register. > > Ontop of this. It is long overdue: > > --- > From: "Borislav Petkov (AMD)" <bp@xxxxxxxxx> > Date: Tue, 28 Nov 2023 14:37:56 +0100 > > Add some initial RAS documentation. The expectation is for this to > collect all the user-visible features for interacting with the RAS > features of the kernel. > In general, does RAS include EDAC and MCE? Thanks. > Signed-off-by: Borislav Petkov (AMD) <bp@xxxxxxxxx> > --- > Documentation/RAS/ras.rst | 26 ++++++++++++++++++++++++++ > Documentation/index.rst | 1 + > 2 files changed, 27 insertions(+) > create mode 100644 Documentation/RAS/ras.rst > -- ~Randy
