> From: Ivan T. Ivanov [mailto:iivanov@xxxxxxxxxx] > Sent: Tuesday, August 20, 2013 8:26 AM > > On Tue, 2013-08-20 at 10:01 -0500, Kumar Gala wrote: > > On Aug 20, 2013, at 9:54 AM, Ivan T. Ivanov wrote: > > > > > > > > Hi, > > > > > > On Tue, 2013-08-20 at 09:33 -0500, Felipe Balbi wrote: > > >> On Tue, Aug 20, 2013 at 05:09:11PM +0300, Ivan T. Ivanov wrote: > > >>> > > >>> On Tue, 2013-08-20 at 08:37 -0500, Felipe Balbi wrote: > > >>>> > > >>>> On Tue, Aug 20, 2013 at 04:32:23PM +0300, Ivan T. Ivanov wrote: > > >>>>> > > >>>>> I think they are SNPS DesignWare PHY's, additionally > > >>>>> wrapped with Qualcomm logic. I could substitute "dwc3" > > >>>>> with just "dw", which will be more correct. > > >>>> > > >>>> alright, thank you. Let's add Paul to the loop since he might have very > > >>>> good insight in the synopsys PHYs. > > >>>> > > >>>> mental note: if any other platform shows up with Synopsys PHY, ask them > > >>>> to use this driver instead :-) > > >>> > > >>> I really doubt that this will bi possible. Control of the PHY's is > > >>> not directly trough ULPI, UTMI or PIPE3 interfaces, but trough > > >>> QSCRATCH registers, which of course is highly Qualcomm specific. > > >> > > >> isn't it a memory mapped IP ? doesn't synopsys provide their own set of > > >> registers ? > > > > > > From what I see it is not directly mapped. How QSCRATCH write and > > > reads transactions are translated to DW IP is unclear to me. > > > > > > I think the question is how does SW access them? > > "USB QSCRATCH Hardware registers" don't ask me what is this :-) > or like Pawel says: "it depends on the SOC" . To answer the question "doesn't synopsys provide their own set of registers", we provide registers in our USB cores to access the PHYs through I2C, ULPI/UTMI, or PIPE3 interfaces. But if someone wants to use our PHY with some other controller that doesn't provide that, then they may need to implement their own register set, as Qualcomm has apparently done. -- Paul ��.n��������+%������w��{.n�����{����* jg��� �����ݢj����G���� ���j:+v���w�m������w�������h�����٥
