On Mon, Jul 03, 2023 at 02:46:45PM +0200, Alexandre Ghiti wrote: > riscv now uses this sysctl so document its usage for this architecture. > > Signed-off-by: Alexandre Ghiti <alexghiti@xxxxxxxxxxxx> > --- > Documentation/admin-guide/sysctl/kernel.rst | 27 ++++++++++++++++++--- > 1 file changed, 23 insertions(+), 4 deletions(-) > > diff --git a/Documentation/admin-guide/sysctl/kernel.rst b/Documentation/admin-guide/sysctl/kernel.rst > index d85d90f5d000..19b627883313 100644 > --- a/Documentation/admin-guide/sysctl/kernel.rst > +++ b/Documentation/admin-guide/sysctl/kernel.rst > @@ -941,16 +941,35 @@ enabled, otherwise writing to this file will return ``-EBUSY``. > The default value is 8. > > > -perf_user_access (arm64 only) > -================================= > +perf_user_access (arm64 and riscv only) > +======================================= > + > +Controls user space access for reading perf event counters. > > -Controls user space access for reading perf event counters. When set to 1, > -user space can read performance monitor counter registers directly. > +arm64 > +===== > > The default value is 0 (access disabled). > > +When set to 1, user space can read performance monitor counter registers > +directly. > + > See Documentation/arm64/perf.rst for more information. > > +riscv > +===== > + > +When set to 0, user space access is disabled. > + > +The default value is 1, user space can read performance monitor counter > +registers through perf, any direct access without perf intervention will trigger > +an illegal instruction. > + > +When set to 2, which enables legacy mode (user space has direct access to cycle > +and insret CSRs only). Note that this legacy value is deprecated and will be > +removed once all user space applications are fixed. > + > +Note that the time CSR is always directly accessible to all modes. > > pid_max > ======= > -- > 2.39.2 > Reviewed-by: Andrew Jones <ajones@xxxxxxxxxxxxxxxx>
