On Fri, Jun 16, 2023 at 2:06 AM Alexandre Ghiti <alexghiti@xxxxxxxxxxxx> wrote:
>
> On Fri, Jun 16, 2023 at 10:43 AM Atish Patra <atishp@xxxxxxxxxxxxxx> wrote:
> >
> > On Fri, May 12, 2023 at 2:03 AM Alexandre Ghiti <alexghiti@xxxxxxxxxxxx> wrote:
> > >
> > > riscv now support mmaping hardware counters so add what's needed to
> > > take advantage of that in libperf.
> > >
> > > Signed-off-by: Alexandre Ghiti <alexghiti@xxxxxxxxxxxx>
> > > ---
> > > tools/lib/perf/mmap.c | 65 +++++++++++++++++++++++++++++++++++++++++++
> > > 1 file changed, 65 insertions(+)
> > >
> > > diff --git a/tools/lib/perf/mmap.c b/tools/lib/perf/mmap.c
> > > index 0d1634cedf44..65f250e0ef92 100644
> > > --- a/tools/lib/perf/mmap.c
> > > +++ b/tools/lib/perf/mmap.c
> > > @@ -392,6 +392,71 @@ static u64 read_perf_counter(unsigned int counter)
> > >
> > > static u64 read_timestamp(void) { return read_sysreg(cntvct_el0); }
> > >
> > > +#elif __riscv_xlen == 64
> > > +
> >
> > This is applicable for RV32 as well. No ?
> > otherwise, you won't need CSR_CYCLEH
>
> Admittedly, I have not checked rv32 at all in this series and the code
> below is a copy-paste. I'd say that rv32 support is out of scope for
> this series, is that ok with you?
>
That's fine. Let's just remove the CYCLEH and leave a TODO comment for RV32.
> >
> > > +#define CSR_CYCLE 0xc00
> > > +#define CSR_TIME 0xc01
> > > +#define CSR_CYCLEH 0xc80
> > > +
> > > +#define csr_read(csr) \
> > > +({ \
> > > + register unsigned long __v; \
> > > + __asm__ __volatile__ ("csrr %0, " #csr \
> > > + : "=r" (__v) : \
> > > + : "memory"); \
> > > + __v; \
> > > +})
> > > +
> > > +static unsigned long csr_read_num(int csr_num)
> > > +{
> > > +#define switchcase_csr_read(__csr_num, __val) {\
> > > + case __csr_num: \
> > > + __val = csr_read(__csr_num); \
> > > + break; }
> > > +#define switchcase_csr_read_2(__csr_num, __val) {\
> > > + switchcase_csr_read(__csr_num + 0, __val) \
> > > + switchcase_csr_read(__csr_num + 1, __val)}
> > > +#define switchcase_csr_read_4(__csr_num, __val) {\
> > > + switchcase_csr_read_2(__csr_num + 0, __val) \
> > > + switchcase_csr_read_2(__csr_num + 2, __val)}
> > > +#define switchcase_csr_read_8(__csr_num, __val) {\
> > > + switchcase_csr_read_4(__csr_num + 0, __val) \
> > > + switchcase_csr_read_4(__csr_num + 4, __val)}
> > > +#define switchcase_csr_read_16(__csr_num, __val) {\
> > > + switchcase_csr_read_8(__csr_num + 0, __val) \
> > > + switchcase_csr_read_8(__csr_num + 8, __val)}
> > > +#define switchcase_csr_read_32(__csr_num, __val) {\
> > > + switchcase_csr_read_16(__csr_num + 0, __val) \
> > > + switchcase_csr_read_16(__csr_num + 16, __val)}
> > > +
> > > + unsigned long ret = 0;
> > > +
> > > + switch (csr_num) {
> > > + switchcase_csr_read_32(CSR_CYCLE, ret)
> > > + switchcase_csr_read_32(CSR_CYCLEH, ret)
> > > + default:
> > > + break;
> > > + }
> > > +
> > > + return ret;
> > > +#undef switchcase_csr_read_32
> > > +#undef switchcase_csr_read_16
> > > +#undef switchcase_csr_read_8
> > > +#undef switchcase_csr_read_4
> > > +#undef switchcase_csr_read_2
> > > +#undef switchcase_csr_read
> > > +}
> > > +
> > > +static u64 read_perf_counter(unsigned int counter)
> > > +{
> > > + return csr_read_num(CSR_CYCLE + counter);
> > > +}
> > > +
> > > +static u64 read_timestamp(void)
> > > +{
> > > + return csr_read_num(CSR_TIME);
> > > +}
> > > +
> > > #else
> > > static u64 read_perf_counter(unsigned int counter __maybe_unused) { return 0; }
> > > static u64 read_timestamp(void) { return 0; }
> > > --
> > > 2.37.2
> > >
> >
> >
> > --
> > Regards,
> > Atish
--
Regards,
Atish
