Gentle ping :)
On 4/13/2023 10:59 PM, K Prateek Nayak wrote:
> commit 66558b730f253 ("sched: Add cluster scheduler level for x86")
> defined cluster on x86 as the set of threads sharing the same L2 cache.
> cluster_id on x86, maps to the l2c_id which currently only Intel
> processors set.
>
> This series sets the l2c_id on AMD and Hygon processors with
> X86_FEATURE_TOPOEXT, using the extended APIC ID and the
> "Cache Properties (L2)" CPUID (0x8000001D EAX). On AMD and Hygon
> processors without X86_FEATURE_TOPOEXT, current behavior will continue.
>
> Following are the changes in value reported by
> "/sys/devices/system/cpu/cpuX/topology/cluster_id" on a 2P Milan system
> (2 x 64C/128T) where L2 is per-core and SMT sibling of CPU (X) is
> CPU ((X + 128) % 256).
>
> - tip:x86/core
>
> $ for i in {0..255}; do\
> echo -n "CPU$i cluster_id: ";\
> cat /sys/devices/system/cpu/cpu$i/topology/cluster_id;\
> done;
>
> CPU0 cluster_id: 65535
> CPU1 cluster_id: 65535
> CPU2 cluster_id: 65535
> CPU3 cluster_id: 65535
> CPU4 cluster_id: 65535
> ...
> CPU254 cluster_id: 65535
> CPU255 cluster_id: 65535
>
> - tip:x86/core + this series
>
> $ for i in {0..255}; do\
> echo -n "CPU$i cluster_id: ";\
> cat /sys/devices/system/cpu/cpu$i/topology/cluster_id;\
> done;
>
> CPU0 cluster_id: 0
> CPU1 cluster_id: 1
> CPU2 cluster_id: 2
> CPU3 cluster_id: 3
> CPU4 cluster_id: 4
> CPU5 cluster_id: 5
> CPU6 cluster_id: 6
> CPU7 cluster_id: 7
> CPU8 cluster_id: 8
> ...
> CPU126 cluster_id: 126
> CPU127 cluster_id: 127
> CPU128 cluster_id: 0
> CPU129 cluster_id: 1
> CPU130 cluster_id: 2
> CPU131 cluster_id: 3
> CPU132 cluster_id: 4
> CPU133 cluster_id: 5
> CPU134 cluster_id: 6
> CPU135 cluster_id: 7
> CPU136 cluster_id: 8
> ...
> CPU254 cluster_id: 126
> CPU255 cluster_id: 127
>
> Note: Hygon maintainer Pu Wen <puwen@xxxxxxxx> has confirmed that the
> same strategy of setting l2c_id works for Hygon as well without
> requiring any change to the function
> (https://lore.kernel.org/lkml/20230411122348.GAZDVRVNvbbS8F5NUB@fat_crate.local/)
> Call to the same function has been added in the Hygon topology init path
> too. Pu Wen, can you please test this version too and let me know if the
> behavior is still as expected.
>
> The series also adds documentation for clusters on x86 platforms and
> applies cleanly on top of tip:x86/core at commit ce3ba2af9695
> ("x86: Suppress KMSAN reports in arch_within_stack_frames()")
>
> ---
> o v1->v2
> - Improved documentation of cluster based on Peter's suggestion.
> - Renamed cacheinfo_amd_init_l2c_id() to
> cacheinfo_topoext_init_l2c_id() and added the call to same in
> Hygon's topology init path.
> - Collected tags for Patch 1.
> ---
> K Prateek Nayak (2):
> arch/x86: Set L2 Cache ID on AMD and Hygon processors
> x86/Documentation: Add documentation about cluster
>
> Documentation/x86/topology.rst | 27 ++++++++++++++++++++++++
> arch/x86/include/asm/cacheinfo.h | 1 +
> arch/x86/kernel/cpu/amd.c | 1 +
> arch/x86/kernel/cpu/cacheinfo.c | 36 ++++++++++++++++++++++++++++++++
> arch/x86/kernel/cpu/hygon.c | 1 +
> 5 files changed, 66 insertions(+)
>
--
Thanks and Regards,
Prateek
