On 07/08/2013 05:33 PM, Ruchika Kharwar wrote: > > On 07/08/2013 02:28 AM, Felipe Balbi wrote: >> On Fri, Jun 21, 2013 at 10:46:10AM -0500, Ruchika Kharwar wrote: >>> Addition of the M and N recommended values for the USB3 PHY DPLL. >>> Sysclk for DRA7xx is 20MHz. >>> This yields: >>> Clk = 20MHz * M/(N+1) = 20MHz * 1000 /(7+1) = 2.5 Ghz >>> >>> Signed-off-by: Nikhil Devshatwar <nikhil.nd@xxxxxx> >>> Signed-off-by: Ruchika Kharwar <ruchika@xxxxxx> >> this won't apply since you had already sent me another version. Please >> send in a fix up patch if that's wrong. >> > I already did .. :-) > Sent 07/04/2013 FYI, I've just sent a better version to fix the root of the problem, i.e. use lookup table instead of index based lookup. That should avoid such problems in the future. cheers, -roger -- To unsubscribe from this list: send the line "unsubscribe linux-doc" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
