On Tue, Apr 05, 2022 at 09:04:04AM +0100, Mark Brown wrote: > On Mon, Apr 04, 2022 at 02:18:58PM -0700, Peter Collingbourne wrote: > > > + For CPUs with the Memory Tagging Extension feature: > > + > > + - If EL3 is present: > > + > > + - SCR_EL3.ATA (bit 26) must be initialised to 0b1. > > + > > + - If the kernel is entered at EL1 and EL2 is present: > > + > > + - HCR_EL2.ATA (bit 56) must be initialised to 0b1. > > Very nitpicky but this is only required for FEAT_MTE2 and above, plain > FEAT_MTE doesn't have these traps. I don't know that this is a thing > that anyone's actually implemented I think that's a valid point. CPUs may implement FEAT_MTE2 but downgrade it to FEAT_MTE if the SoC does not provide allocation tag storage. So we should make it clear here that only from FEAT_MTE2 we should set those bits (ID_AA64PFR1_EL1.MTE >= 2), otherwise they should be 0 or hyp/firmware risks the OS triggering random external aborts. > and from v8.7 on it's not permitted but the above isn't strictly true > if someone did for some reason have the most basic version. The wording is tricky: "This feature is mandatory from Armv8.7 when FEAT_MTE2 is implemented". So one can still implement FEAT_MTE (or none at all). -- Catalin
