On Wed, Apr 07, 2021 at 04:29:12PM +0200, Christoph Müllner wrote: > RISC-V defines LR/SC loops consisting of up to 16 instructions as > constrained LR/SC loops. Such constrained LR/SC loops provide the > required forward guarantees, that are expected (similar to what other > architectures, like AArch64, have). The text quoted by others didn't seem to say such a thing, but whatever. > What RISC-V does not have is sub-word atomics and if required, we > would have to implement them as LL/SC sequences. And yes, using atomic > instructions is preferred over using LL/SC, (psudo asm, can't be bothered to figure out the actual syntax) # setup r_and_mask, r_or_mask .L1 LL r, [word] AND r, r, r_and_mask OR r, r, r_or_mask SC r, [word] JNE .L1 is what you need for LL/SC based xchg16, that's less than 16 instructions. If RISC-V guarantees fwd progress on that, good, write it like that and lets end this thread. The fact that this is apparently hard, is not good.
