On Fri, 28 Jun 2024 01:54:00 +0800
Chen-Yu Tsai <wens@xxxxxxxx> wrote:
Hi Chen-Yu,
> On Tue, Jun 25, 2024 at 7:23 AM Andre Przywara <andre.przywara@xxxxxxx> wrote:
> >
> > The Allwinner H616 SoC contains a crypto engine very similar to the H6
> > version, but with all base addresses in the DMA descriptors shifted by
> > two bits. This requires a new compatible string.
> > Also the H616 CE relies on the internal osciallator for the TRNG
> > operation, so we need to reference this clock.
> >
> > Signed-off-by: Andre Przywara <andre.przywara@xxxxxxx>
> > ---
> > arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi | 10 ++++++++++
> > 1 file changed, 10 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
> > index 921d5f61d8d6a..187663d45ed72 100644
> > --- a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
> > +++ b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
> > @@ -113,6 +113,16 @@ soc {
> > #size-cells = <1>;
> > ranges = <0x0 0x0 0x0 0x40000000>;
> >
> > + crypto: crypto@1904000 {
> > + compatible = "allwinner,sun50i-h616-crypto";
> > + reg = <0x01904000 0x1000>;
>
> The address range only goes up to 0x019047ff. The other half is the
> secure crypto engine. The other bits look correct.
You are right, the manual restricts CE_NS to 0x019047ff, and we certainly
use much less registers than that anyway. So good catch!
> I can fix this up when applying, assuming the driver parts get merged
> in the next few days.
Many thanks, I'd be very grateful if you could fix this up!
Cheers,
Andre
>
> Chenyu
>
> > + interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>,
> > + <&ccu CLK_MBUS_CE>, <&rtc CLK_IOSC>;
> > + clock-names = "bus", "mod", "ram", "trng";
> > + resets = <&ccu RST_BUS_CE>;
> > + };
> > +
> > syscon: syscon@3000000 {
> > compatible = "allwinner,sun50i-h616-system-control";
> > reg = <0x03000000 0x1000>;
> > --
> > 2.39.4
> >
