On 6/5/24 11:02 PM, Jarkko Sakkinen wrote:
On Wed Jun 5, 2024 at 10:03 PM EEST, wrote:
So I did not mean to imply that DRTM support on various
platforms/architectures has a short expiration date. In fact we are
actively working on DRTM support through the TrenchBoot project on
several platforms/architectures. Just a quick rundown here:
Intel: Plenty of Intel platforms are vPro with TXT. It is really just
the lower end systems that don't have it available (like Core i3). And
my guess was wrong about x86s. You can find the spec on the page in the
following link. There is an entire subsection on SMX support on x86s and
the changes to the various GETSEC instruction leaves that were made to
make it work there (see 3.15).
https://urldefense.com/v3/__https://www.intel.com/content/www/us/en/developer/articles/technical/envisioning-future-simplified-architecture.html__;!!ACWV5N9M2RV99hQ!Lt-srkRLHstA9PPCB-NWogvHP-9mfh2bHjkml-lARY79BhYlWJjhrHb6RyCN_WdGstcABq1FdqPUKn5dCdw$
Happend to bump into same PDF specification and exactly the seeked
information is "3.15 SMX Changes". So just write this down to some
patch that starts adding SMX things.
Link: https://urldefense.com/v3/__https://cdrdv2.intel.com/v1/dl/getContent/776648__;!!ACWV5N9M2RV99hQ!Lt-srkRLHstA9PPCB-NWogvHP-9mfh2bHjkml-lARY79BhYlWJjhrHb6RyCN_WdGstcABq1FdqPUuZy8Sfk$
So link and document, and other stuff above is not relevant from
upstream context, only potential maintenance burden :-)
I am not 100% sure what you mean exactly here...
For any architectures dig a similar fact:
1. Is not dead.
2. Will be there also in future.
Make any architecture existentially relevant for and not too much
coloring in the text that is easy to check.
It is nearing 5k lines so you should be really good with measured
facts too (not just launch) :-)
... but overall I get your meaning. We will spend time on this sort of
documentation for the v10 release.
Thanks for the feedback,
Ross
BR, Jarkko
