Hi Ard, Thanks for responding! > > For the situation where this problem is occuring, the actual buffers are stored inside > > the ahash_req structure. So my question is: is there any reason why this structure may > > not be DMA-able on some systems? (as I have a hunch that may be the problem ...) > > > > If DMA is non-coherent, and the ahash_req structure is also modified > by the CPU while it is mapped for DMA, you are likely to get a > conflict. > Ah ... I get it. If I dma_map TO_DEVICE then all relevant cachelines are flushed, then if the CPU accesses any other data sharing those cachelines, they get read back into the cache. Any subsequent access of the actual result will then read stale data from the cache. > It should help if you align the DMA-able fields sufficiently, and make > sure you never touch them while they are mapped for writing by the > device. > Yes, I guess that is the only way. I also toyed with the idea of using dedicated properly dma_alloc'ed buffers with pointers in the ahash_request structure, but I don't see how I can allocate per-request buffers as there is no callback to the driver on req creation. So ... is there any magical way within the Linux kernel to cacheline-align members of a structure? Considering cacheline size is very system-specific? Regards, Pascal van Leeuwen Silicon IP Architect Multi-Protocol Engines, Rambus Security Rambus ROTW Holding BV +31-73 6581953 Note: The Inside Secure/Verimatrix Silicon IP team was recently acquired by Rambus. Please be so kind to update your e-mail address book with my new e-mail address. ** This message and any attachments are for the sole use of the intended recipient(s). It may contain information that is confidential and privileged. If you are not the intended recipient of this message, you are prohibited from printing, copying, forwarding or saving it. Please delete the message and attachments and notify the sender immediately. ** Rambus Inc.<http://www.rambus.com>
