On Fri, Jun 23, 2017 at 07:33:20AM +0000, Radu Solea wrote: > > Normally I would agree with you, if it's a weird requirement coming > from hardware or driver. In this case I think it's different. This is > not a limitation coming from one driver or one particular hardware > variety. It applies to all platforms that do not have hw cache > coherence and a large enough cacheline. > > A couple of lines below the allocation hash is linked into a > scatterlist, a data structure with remarkably high chances of ending up > in a DMA endpoint, yet we choose to ignore all other DMA requirements? What I'm saying is that you cannot rely on crypto API users to do this for you. Sure we can fix this one spot in gcm.c. But any other user of caam anywhere in the kernel can do exactly the same thing. You cannot expect them to know to allocate IVs at cacheline boundaries. So if you have this requirement (which the generic C version certainly does not), then you'll need to deal with it in the driver. Of course if every DMA driver needed to do the same thing, then it's something the crypto API should take care of, e.g., like we do for alignmask. Cheers, -- Email: Herbert Xu <herbert@xxxxxxxxxxxxxxxxxxx> Home Page: http://gondor.apana.org.au/~herbert/ PGP Key: http://gondor.apana.org.au/~herbert/pubkey.txt
