Hello, On Tue, 23 May 2017 12:13:28 +0100, Marc Zyngier wrote: > > The crypto block being in the CP part, it has a wired interrupt to the > > ICU (also in the CP). The ICU then turns this wired interrupt into a > > memory write transaction to a register called GICP SPI in the AP, which > > triggers a SPI interrupt in the GIC. > > Is that some kind of Level-triggered MSI, à la GICv3 GICD_SETSPI_NSR? It is some kind of MSI, and the registers are called GICP_SETSPI/GICP_CLRSPI, so I would assume it's quite similar to this GICv3 feature. > > However, I have a patch series that I plan to submit hopefully in the > > next days that adds an ICU driver, and changes the Device Tree to refer > > to the ICU interrupt instead. > > OK, I'm quite interested to see that, specially if my above hunch is > right... I'll send the patches soon. I'm sure there will be lots of comments :) Best regards, Thomas -- Thomas Petazzoni, CTO, Free Electrons Embedded Linux and Kernel engineering http://free-electrons.com
