On 1/12/2016 5:14 PM, Horia Geantă wrote:
> The following patches increase/fix CAAM performance by modifying
> the configuration of MCFGR (Master Configuration Register):
> -1st patch fixes a ~ 5% performance drop on PPC platforms
> -2nd patch improves performance in some use cases, since CAAM DMA
> transfers are optimized
>
>
> Note: AWCACHE[0] (AXI3 "bufferable") and AWCACHE[1] (AXI3 "cacheable")
> are set irrespective of platform, since:
> -for ARM-based SoCs: the interconnect IP ignores AWCACHE[0]
> -for PPC-based SoCs: PAMU handles coherency control, not AWCACHE[1]
>
> Horia Geantă (2):
> crypto: caam - make write transactions bufferable on PPC platforms
> crypto: caam - enable LARGE_BURST for enhancing DMA transactions size
Herbert, I see that you've sent the crypto fixes for 4.5 pull request.
Any reason why these patches were not included?
I was expecting at least the first one to get it, it's even Cc-ing stable.
Thanks,
Horia
��.n��������+%������w��{.n�����{���{ay� ʇڙ���f���h������_�(�階�ݢj"��������G����?���&��
