Re: [RFC PATCH 0/3] support for interleaving in generic chaining modes

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On 7 February 2014 10:44, Herbert Xu <herbert@xxxxxxxxxxxxxxxxxxx> wrote:
> On Fri, Feb 07, 2014 at 10:42:14AM +0100, Ard Biesheuvel wrote:
>>
>> Another example is bit sliced AES like the implementation in
>> arch/arm/crypto. It is 45% faster than the ordinary ARM asm
>> implementation, but its natural chunk size is 8 blocks. Passing fewer
>> blocks hurts performance, while passing more blocks does not give any
>> additional benefit at all.
>>
>> So in many cases, it would be good to know the preferred chunk size of
>> an algorithm.
>
> So are there cases where passing more blocks hurt the performance
> or not?
>

>From the point of the core algo implementation, probably not, it just
levels off asymptotically.

So i get your point: I will have a go at passing the entire buffer to
ecb(%s), and then wrapping the chaining mode around that.
I guess you don't think the (avoidable) additional memory usage is a concern?

-- 
Ard.
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