Re: [RFC PATCH 0/3] support for interleaving in generic chaining modes

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On Fri, Feb 07, 2014 at 10:42:14AM +0100, Ard Biesheuvel wrote:
>
> Another example is bit sliced AES like the implementation in
> arch/arm/crypto. It is 45% faster than the ordinary ARM asm
> implementation, but its natural chunk size is 8 blocks. Passing fewer
> blocks hurts performance, while passing more blocks does not give any
> additional benefit at all.
> 
> So in many cases, it would be good to know the preferred chunk size of
> an algorithm.

So are there cases where passing more blocks hurt the performance
or not?

Cheers,
-- 
Email: Herbert Xu <herbert@xxxxxxxxxxxxxxxxxxx>
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