Add ECC feature support to Tx and Rx FIFOs for Xilinx CAN Controller. ECC is an IP configuration option where counter registers are added in IP for 1bit/2bit ECC errors count and reset. Also driver reports 1bit/2bit ECC errors for FIFOs based on ECC error interrupts. Add xlnx,has-ecc optional property for Xilinx AXI CAN controller to support ECC if the ECC block is enabled in the HW. Add ethtool stats interface for getting all the ECC errors information. There is no public documentation for it available. --- BRANCH: linux-can-next/master Changes in v7: Update with spinlock only for stats counters Changes in v6: Update commit description Changes in v5: Fix review comments Change the sequence of updates the stats Add get_strings and get_sset_count stats interface Use u64 stats helper function Changes in v4: Fix DT binding check warning Update xlnx,has-ecc property description Changes in v3: Update mailing list Update commit description Changes in v2: Address review comments Add ethtool stats interface Update commit description Srinivas Goud (3): dt-bindings: can: xilinx_can: Add 'xlnx,has-ecc' optional property can: xilinx_can: Add ECC support can: xilinx_can: Add ethtool stats interface for ECC errors .../devicetree/bindings/net/can/xilinx,can.yaml | 5 + drivers/net/can/xilinx_can.c | 159 ++++++++++++++++++++- 2 files changed, 160 insertions(+), 4 deletions(-) -- 2.1.1
