On 23.06.2023 09:48:16, Michal Simek wrote: > Hi Marc, > > On 6/16/23 13:12, Marc Kleine-Budde wrote: > > On 12.06.2023 17:12:54, Srinivas Goud wrote: > > > ECC feature added to Tx and Rx FIFO’s for Xilinx CAN Controller. > > > Part of this feature configuration and counter registers added > > > in Xilinx CAN Controller for 1bit/2bit ECC errors count and reset. > > > Please find more details in PG096 v5.1 document. > > > > The document "PG096 (v5.1) May 16, 2023 CAN v5.1" [1] lists the > > XCAN_ECC_CFG_OFFSET as reserved, although it has a section "ECC > > Configuration Register". > > > > [1] https://docs.xilinx.com/viewer/book-attachment/Bv6XZP9HRonCGi58fl10dw/ch1ZLpOt4UKWNub7DXjJ7Q > > > > The other registers (XCAN_TXTLFIFO_ECC_OFFSET, XCAN_TXOLFIFO_ECC_OFFSET, > > XCAN_TXOLFIFO_ECC_OFFSET) are also listed as reserved and not even > > mentioned on the document. Am I missing something? > > We cross check available public documentation with HW team and there is no > public documentation for this feature yet. We didn't get any exact day when > documentation is going to be released. It's a pity, but's that the way it's sometimes is. > Unfortunately it is not the first or even last time when this is happening > but I still think is good to get this feature done properly till the time > when documentation catch it up. Please let me know if you have any concern > about it. No problem, update the cover letter and mention that the documentation is not public available, yet. For reference we can keep the reference to the internal doc (and mention that). regards, Marc -- Pengutronix e.K. | Marc Kleine-Budde | Embedded Linux | https://www.pengutronix.de | Vertretung Nürnberg | Phone: +49-5121-206917-129 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-9 |
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