On 12.06.2023 17:12:54, Srinivas Goud wrote: > ECC feature added to Tx and Rx FIFO’s for Xilinx CAN Controller. > Part of this feature configuration and counter registers added > in Xilinx CAN Controller for 1bit/2bit ECC errors count and reset. > Please find more details in PG096 v5.1 document. The document "PG096 (v5.1) May 16, 2023 CAN v5.1" [1] lists the XCAN_ECC_CFG_OFFSET as reserved, although it has a section "ECC Configuration Register". [1] https://docs.xilinx.com/viewer/book-attachment/Bv6XZP9HRonCGi58fl10dw/ch1ZLpOt4UKWNub7DXjJ7Q The other registers (XCAN_TXTLFIFO_ECC_OFFSET, XCAN_TXOLFIFO_ECC_OFFSET, XCAN_TXOLFIFO_ECC_OFFSET) are also listed as reserved and not even mentioned on the document. Am I missing something? regards, Marc -- Pengutronix e.K. | Marc Kleine-Budde | Embedded Linux | https://www.pengutronix.de | Vertretung Nürnberg | Phone: +49-5121-206917-129 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-9 |
Attachment:
signature.asc
Description: PGP signature
