On 14/06/2023 12:22, Goud, Srinivas wrote: > Hi, > >> -----Original Message----- >> From: Marc Kleine-Budde <mkl@xxxxxxxxxxxxxx> >> Sent: Tuesday, June 13, 2023 1:23 PM >> To: Goud, Srinivas <srinivas.goud@xxxxxxx> >> Cc: wg@xxxxxxxxxxxxxx; davem@xxxxxxxxxxxxx; edumazet@xxxxxxxxxx; >> kuba@xxxxxxxxxx; pabeni@xxxxxxxxxx; gcnu.goud@xxxxxxxxx; git (AMD- >> Xilinx) <git@xxxxxxx>; michal.simek@xxxxxxxxxx; linux-can@xxxxxxxxxxxxxxx; >> linux-arm-kernel@xxxxxxxxxxxxxxxxxxx; linux-kernel@xxxxxxxxxxxxxxx >> Subject: Re: [PATCH 1/3] dt-bindings: can: xilinx_can: Add ECC property >> ‘xlnx,has-ecc’ >> >> On 12.06.2023 17:12:55, Srinivas Goud wrote: >>> ECC feature added to Tx and Rx FIFO’s for Xilinx CAN Controller. >>> Part of this feature configuration and counter registers added in IP >>> for 1bit/2bit ECC errors. >>> Please find more details in PG096 v5.1 document. >>> >>> xlnx,has-ecc is optional property and added to Xilinx CAN Controller >>> node if ECC block enabled in the HW. >>> >>> Signed-off-by: Srinivas Goud <srinivas.goud@xxxxxxx> >> >> Is there a way to introspect the IP core to check if this feature is compiled in? > There is no way(IP registers) to indicate whether ECC feature is enabled or not. Isn't this then deductible from compatible? Your binding claims it is only for AXI CAN, so xlnx,axi-can-1.00.a, even though you did not restrict it in the binding. Best regards, Krzysztof
