> Taken from one of your traces is data below We have a tef fifo size of 4, so yeah in this scenario it's expected to have TEF full situations. A larger > TEF/Faster SPI/better SPI utilization would all reduce the occurrence of the issue. I was pretty sure that my application never has more than three frames on the fly - having sent three frames I wait for the first to be arrived before I sent the next. However, it seems that the RX IRQ processing is faster than than the TX IRQ processing and I am sending the next frame when the TX event fifo has not yet been read. As "buffer full" is no error (as opposed to buffer overflow), should this really be a non debug kernel message? Some other means of getting such statistics appreciated (see my posting " mcp251xfd diagnostic outputs"). -- Stefan
