On 19.01.2023 07:47:44, Stefan Althöfer wrote:
> > Before this change the driver used to read the RX FIFO head from the chip
> > (it points to the index that is **written** to next by the driver).
>
> Read?
Doh, it should read:
it points to the index that is written to next by the *chip*.
> My concern was about such a situation
>
> 3 1 2
> --------------------
> N|N|O|O|O|0|N|N|N|N|
> --------------------
What's the meaning of 'N', 'O' and '0' (zero)?
> Correct fifo head is [1]. What are the potential false reads?
> Is it possible that a false read of fifo head will point to [2].
>
> In cases that I have seen it had pointed to older messages always
> e.g. [3].
| 4 3 1 2
| --------------------
| N|N|O|O|O|O|N|N|N|N|
| --------------------
If N means new, and O means old (I've replaced the 0 by O), then the
correct head would be [4]. That's the index the chip will write the next
RX'ed CAN frame. The chip's tail index would point to [1]. That means
all CAN frames between [1] (including) and [4] (excluding) are new and
must be read.
If the driver reads a wrong FIFO head, there are 2 possibilities:
a) driver reads FIFO head [2]
- all frames between [1] (including) and [2] excluding are read and
pushed into the networking stack (denoted by [R]):
| 4 3 1 2
| --------------------
| N|N|O|O|O|O|N|N|N|N|
| --------------------
| R R
- 2 frames are marked as read, the chip's tail pointer will advance
from [1] to [2].
| 4 3 1 2
| --------------------
| N|N|O|O|O|O|O|O|N|N|
| --------------------
|
- the RX interrupt stays active, as the RX FIFO is not empty
- the usual RX IRQ handling takes place and the rest of the CAN
frames are read.
| 4 3 1 2
| --------------------
| O|O|O|O|O|O|O|O|O|O|
| --------------------
|
- the chip's tail index is correct [4]
- the erratum results in a higher latency, as the driver could
have handled 4 RX CAN frames in one burst instead of 2.
b) driver reads FIFO head [3]
- all frames between [1] (including) end of FIFO are read and
pushed into the networking stack (denoted by [R]):
| 4 3 1 2
| --------------------
| N|N|O|O|O|O|N|N|N|N|
| --------------------
| R R R R
- 4 frames are marked as read, the chip's tail pointer will advance
from [1] to [5].
| 5 4 3 1 2
| --------------------
| N|N|O|O|O|O|O|O|O|O|
| --------------------
|
- all frames between [5] (including) end [3] (excluding) are read
| 5 4 3 1 2
| --------------------
| N|N|O|O|O|O|O|O|O|O|
| --------------------
| R R R
- during the iteration the driver sees an old timestamp for the 3rd
CAN frame and stops processing there
- although 3 CAN frames have been read from the FIFO, only 2 have
been processes and pushed to the networking stack
- 2 frames are marked as read, the chip's tail index will advance
from [5] to [4].
| 5 4 3 1 2
| --------------------
| O|O|O|O|O|O|O|O|O|O|
| --------------------
|
- the chip's tail index is correct [4]
- the overhead due to the erratum was the longer SPI read of the last
CAN RX frame and the additional processing time (which is probably
neglectable compared to the SPI overhead).
regards,
Marc
--
Pengutronix e.K. | Marc Kleine-Budde |
Embedded Linux | https://www.pengutronix.de |
Vertretung West/Dortmund | Phone: +49-231-2826-924 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
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