Hi, > With the help of Thomas we found out that the chip has a time window after receiving a CAN frame where the RX FIFO STA register content is not read correctly. Does the workaround assume that most of the messages in the fifo are old (already read) content? What happens if there is mostly new (not yet read) content in the fifo? Suppose a slow host or coalescing. Can the temporarily incorrect RX FIFO STA register point to one of those (ahead of next-to-read)? Wouldn't we drop messages or cause a deadlock then? -- Stefan
