Hi Marc,
sorry for the delay.
On Mon, Dec 12, 2022 at 11:54:44AM +0100, Marc Kleine-Budde wrote:
> On 06.12.2022 17:20:01, Marc Kleine-Budde wrote:
> > On 06.12.2022 12:57:28, Markus Schneider-Pargmann wrote:
> > > Specify exactly which registers are read/writeable in the chip. This
> > > is supposed to help detect any violations in the future.
> > >
> > > Signed-off-by: Markus Schneider-Pargmann <msp@xxxxxxxxxxxx>
> > > ---
> > > drivers/net/can/m_can/tcan4x5x-regmap.c | 43 +++++++++++++++++++++----
> > > 1 file changed, 37 insertions(+), 6 deletions(-)
> > >
> > > diff --git a/drivers/net/can/m_can/tcan4x5x-regmap.c b/drivers/net/can/m_can/tcan4x5x-regmap.c
> > > index 33aed989e42a..2b218ce04e9f 100644
> > > --- a/drivers/net/can/m_can/tcan4x5x-regmap.c
> > > +++ b/drivers/net/can/m_can/tcan4x5x-regmap.c
> > > @@ -90,16 +90,47 @@ static int tcan4x5x_regmap_read(void *context,
> > > return 0;
> > > }
> > >
> > > -static const struct regmap_range tcan4x5x_reg_table_yes_range[] = {
> > > +static const struct regmap_range tcan4x5x_reg_table_wr_range[] = {
> > > + /* Device ID and SPI Registers */
> > > + regmap_reg_range(0x000c, 0x0010),
> >
> > According to "Table 8-8" 0xc is RO, but in "8.6.1.4 Status (address =
> > h000C) [reset = h0000000U]" it clearly says it has write 1 to clear bits
> > :/.
I am trying to clarify this. I guess table 8-8 is not correct, but we
will see.
> >
> > > + /* Device configuration registers and Interrupt Flags*/
> > > + regmap_reg_range(0x0800, 0x080c),
> > > + regmap_reg_range(0x0814, 0x0814),
> >
> > 0x814 is marked as reserved in "SLLSEZ5D – JANUARY 2018 – REVISED JUNE
> > 2022"?
>
Yes that's a mistake, sorry. I will add a fixup for the upcoming series.
> I'll take the series as is, that can be fixed later.
Thank you!.
Best,
Markus
