On 24.03.2022 12:28:10, Thomas.Kopp@xxxxxxxxxxxxx wrote: > Hrm, good point. Now with frequency scaling set to performance I don't > see the difference anymore and see a consistent 2 SPI interrupts per > CAN-FD message. So at least in performance mode this seems to be the > same. Would be interesting to see the effects on a weaker system than > the Pi4. > > In CAN-FD mode I can't get the driver to allocate less than 1 Fifo > with a depth of 16 to RX. Is that intended? Yes, take a look at: | const struct can_ram_config mcp251xfd_ram_config The struct describes the hardware and gives configuration constraints. E.g. the minimum RX is set to 16. > I.e. I try to use ethtool -G can0 rx 8 tx 8 and it still leads to the > following setup: > > FIFO setup: TEF: 0x400: 8*12 bytes = 96 bytes > FIFO setup: RX-0: FIFO 1/0x418: 16*76 bytes = 1216 bytes > FIFO setup: TX: FIFO 2/0x8d8: 8*72 bytes = 576 bytes > FIFO setup: free: 160 bytes From my point of view a lower value for RX brings more negative impact (RX FIFO overflows, etc...), than the increase of TX buffers from 8 to 16 brings positive impact (increased CAN bus load). If there are use cases where 16 TX buffers are beneficial, I'm happy to discuss them and change the defaults. BTW: There are other/better TX optimizations options like implementing TX byte queue limits with netdev_xmit_more() support. regards, Marc -- Pengutronix e.K. | Marc Kleine-Budde | Embedded Linux | https://www.pengutronix.de | Vertretung West/Dortmund | Phone: +49-231-2826-924 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
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