> > Yes, will do. For the record, the difference was really marginal. On > > 20k frames I had 39182 vs. 39139 SPI interrupts. > > I assume in some case the RX processing took so long that there was > another RX CAN frame ready in the same IRQ handler run. Hrm, good point. Now with frequency scaling set to performance I don't see the difference anymore and see a consistent 2 SPI interrupts per CAN-FD message. So at least in performance mode this seems to be the same. Would be interesting to see the effects on a weaker system than the Pi4. In CAN-FD mode I can't get the driver to allocate less than 1 Fifo with a depth of 16 to RX. Is that intended? I.e. I try to use ethtool -G can0 rx 8 tx 8 and it still leads to the following setup: FIFO setup: TEF: 0x400: 8*12 bytes = 96 bytes FIFO setup: RX-0: FIFO 1/0x418: 16*76 bytes = 1216 bytes FIFO setup: TX: FIFO 2/0x8d8: 8*72 bytes = 576 bytes FIFO setup: free: 160 bytes Best Regards, Thomas
