On Mon, 2021-11-15 at 10:18 +0100, Matthias Schiffer wrote: > This series fixes two issues we found with the setup of the CAN > controller of Intel Elkhart Lake CPUs: > > - Patch 1 fixes an incorrect reference clock rate, which caused the > configured and the actual bitrate always to differ by a factor of 2. > - Patches 2-4 fix a deviation between the driver and the documentation. > We did not actually see issues without these patches, however we did > only superficial testing and may just not have hit the specific > bittiming values that violate the documented limits. > > > Matthias Schiffer (4): > can: m_can: pci: fix incorrect reference clock rate > Revert "can: m_can: remove support for custom bit timing" > can: m_can: make custom bittiming fields const > can: m_can: pci: use custom bit timings for Elkhart Lake > > drivers/net/can/m_can/m_can.c | 24 ++++++++++++---- > drivers/net/can/m_can/m_can.h | 3 ++ > drivers/net/can/m_can/m_can_pci.c | 48 ++++++++++++++++++++++++++++--- > 3 files changed, 65 insertions(+), 10 deletions(-) > I just noticed that m_can_pci is completely broken on 5.15.2, while it's working fine on 5.14.y. I assume something simliar to [1] will be necessary in m_can_pci as well, however I'm not really familiar with the driver. There is no "mram_base" in m_can_plat_pci, only "base". Is using "base" with iowrite32/ioread32 + manual increment the correct solution here? [1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=99d173fbe8944861a00ebd1c73817a1260d21e60
