> Von: Marc Kleine-Budde <mkl@xxxxxxxxxxxxxx>
> Gesendet: Sonntag, 6. Dezember 2020 21:49
>
> On 12/6/20 9:36 PM, Sven Schuchmann wrote:
> >> -----Ursprüngliche Nachricht-----
> >> Von: Marc Kleine-Budde <mkl@xxxxxxxxxxxxxx>
> >> Gesendet: Sonntag, 6. Dezember 2020 21:15
> >>>> As it's now working in general, Sven can test from setup under Linux.
> >>>
> >>> if I try to load under linux with:
> >>> sudo dtoverlay mcp251xfd spi0-0 interrupt=25
> >>>
> >>> I get:
> >>> [ 36.154548] CAN device driver interface
> >>> [ 36.158644] mcp251xfd spi0.0: No Oscillator (clock) defined.
> >>
> >> The clock is missing. Let's see if it is added to the DT.
> >>
> >> Do a diff of the DT before and after applying the overlay.
> >>
> >> | sudo dtc -I fs /proc/device-tree -o before
> >> | sudo dtoverlay mcp251xfd spi0-0 interrupt=25
> >> | sudo dtc -I fs /proc/device-tree -o after
> >> | diff -u before after
> >>
> >> Send the output of the diff.
> > Here is the diff:
> > --- before 2020-12-06 20:31:40.430361119 +0000
> > +++ after 2020-12-06 20:32:35.939656243 +0000
> > @@ -35,6 +35,13 @@
> > clock-frequency = < 0x337f980 >;
> > };
> >
> > + mcp251xfd-spi0-0-osc {
> > + compatible = "fixed-clock";
> > + #clock-cells = < 0x00 >;
> > + phandle = < 0xde >;
> ^^^^^^^^
> > + clock-frequency = < 0x2625a00 >;
> > + };
> > +
> > clk-usb {
> > compatible = "fixed-clock";
> > #clock-cells = < 0x00 >;
> > @@ -1029,6 +1036,12 @@
> > brcm,function = < 0x04 >;
> > };
> >
> > + mcp251xfd_spi0_0_pins {
> > + brcm,pins = < 0x19 >;
> > + phandle = < 0xdd >;
> > + brcm,function = < 0x00 >;
> > + };
> > +
> > uart1_pins {
> > brcm,pins;
> > phandle = < 0x15 >;
> > @@ -1546,6 +1559,18 @@
> > dmas = < 0x0b 0x06 0x0b 0x07 >;
> > pinctrl-names = "default";
> >
> > + mcp251xfd@0 {
> > + compatible = "microchip,mcp251xfd";
> > + clocks = < 0xde >;
> ^^^^^^^^
>
> That looks good so far.
>
> > + interrupt-parent = < 0x0f >;
> > + interrupts = < 0x19 0x08 >;
> > + phandle = < 0xdf >;
> > + reg = < 0x00 >;
> > + pinctrl-0 = < 0xdd >;
> > + spi-max-frequency = < 0x1312d00 >;
> > + pinctrl-names = "default";
> > + };
> > +
> > spidev@1 {
> > compatible = "spidev";
> > #address-cells = < 0x01 >;
> > @@ -1557,6 +1582,7 @@
> >
> > spidev@0 {
> > compatible = "spidev";
> > + status = "disabled";
> > #address-cells = < 0x01 >;
> > #size-cells = < 0x00 >;
> > phandle = < 0xa6 >;
>
> Is the clock detcted and loaded by the clock framework?
>
> Can you create a diff for "/sys/kernel/debug/clk/clk_summary" before and after
> loading the overlay?
The diff shows no difference, the output is always:
enable prepare protect duty
clock count count count rate accuracy phase cycle
---------------------------------------------------------------------------------------------
fw-clk-m2mc 0 0 0 120000000 0 0 50000
fw-clk-v3d 0 0 0 250000000 0 0 50000
fw-clk-core 0 0 0 200000000 0 0 50000
fw-clk-arm 0 0 0 600000000 0 0 50000
108MHz-clock 0 0 0 108000000 0 0 50000
otg 0 0 0 480000000 0 0 50000
osc 3 3 0 54000000 0 0 50000
tsens 0 0 0 3375000 0 0 50000
otp 0 0 0 13500000 0 0 50000
timer 0 0 0 1000000 0 0 50000
plld 5 5 0 3000000091 0 0 50000
plld_dsi1 1 1 0 11718751 0 0 50000
plld_dsi0 1 1 0 11718751 0 0 50000
plld_per 2 2 0 750000023 0 0 50000
emmc2 1 1 0 100000003 0 0 50000
emmc 0 0 0 250000007 0 0 50000
uart 0 0 0 48000001 0 0 50000
plld_core 1 1 0 600000019 0 0 50000
pllc 3 3 0 2999999988 0 0 50000
pllc_per 1 1 0 599999998 0 0 50000
pllc_core2 0 0 0 11718750 0 0 50000
pllc_core1 0 0 0 11718750 0 0 50000
pllc_core0 2 2 0 999999996 0 0 50000
vpu 3 3 0 500000000 0 0 50000
aux_spi2 0 0 0 500000000 0 0 50000
aux_spi1 0 0 0 500000000 0 0 50000
aux_uart 0 0 0 500000000 0 0 50000
peri_image 0 0 0 500000000 0 0 50000
plla 2 2 0 2999999988 0 0 50000
plla_ccp2 0 0 0 11718750 0 0 50000
plla_dsi0 0 0 0 11718750 0 0 50000
plla_core 1 1 0 499999998 0 0 50000
h264 0 0 0 499999998 0 0 50000
isp 0 0 0 499999998 0 0 50000
dsi1p 0 0 0 0 0 0 50000
dsi0p 0 0 0 0 0 0 50000
dsi1e 0 0 0 0 0 0 50000
dsi0e 0 0 0 0 0 0 50000
cam1 0 0 0 0 0 0 50000
cam0 0 0 0 0 0 0 50000
dpi 0 0 0 0 0 0 50000
tec 0 0 0 0 0 0 50000
smi 0 0 0 0 0 0 50000
slim 0 0 0 0 0 0 50000
gp2 0 0 0 0 0 0 50000
gp1 0 0 0 0 0 0 50000
gp0 0 0 0 0 0 0 50000
dft 0 0 0 0 0 0 50000
aveo 0 0 0 0 0 0 50000
pcm 0 0 0 0 0 0 50000
pwm 0 0 0 0 0 0 50000
sdram 0 0 0 0 0 0 50000
hsm 0 0 0 0 0 0 50000
vec 0 0 0 0 0 0 50000
Sven
--
Sven Schuchmann
Schleißheimer Soft- und
Hardwareentwicklung GmbH
Am Kalkofen 10
61206 Nieder-Wöllstadt
GERMANY
Phone: +49 6034 9148 711
Fax: +49 6034 9148 91
Email: schuchmann@xxxxxxxxxxxxxxxxx
