On 2/12/20 10:59 AM, Thomas.Kopp@xxxxxxxxxxxxx wrote:
>> On the transition from "TX ERROR_WARNING -> TX ERROR_ACTIVE" the
>> CERRIF is not set.
> Mhm, do I misunderstand your point here?
I misread the documentation somehow.
Hmmm. I think the question is, is there a dedicated warning state and
if, how are the transitions from and to it?
>From my understanding:
-- E > 95 -- -- E > 127 -- -- E > 255 --
/ \ / \ / \
/ V / V / V
--> error active error warning error passive bus off
^ / ^ /
\ / \ /
-- E < 96 -- -- E < 128 --
> The Transition TX ERROR_WARNING -> TX ERROR_ACTIVE isn't covered by
> the CERRIF interrupt (which matches the documentation).
ACK. The documentation talks about error passive to error active, which
means the diagram looks like this:
-- E > 95 -- -- E > 127 -- -- E > 255 --
/ \ / \ / \
/ V / V / V
--> error active error warning error passive bus off
^ /
\ /
------------------- E < 128 --
> The interrupt bit gets set on ERROR_Passive to ERROR_ACTIVE (TEC/REC
> goes from 128 to 127).
I think we have to discuss how the state diagram on socketcan should
look like.
> At that transition I do see the CERRIF bit. It is correct and
> intended (though maybe not 100% intuitive) that going from
> ERROR_WARNING to ERROR_ACTIVE TEC/REC 96 to 95 CERRIF is NOT being
> set.
Ok.
regards
Marc
--
Pengutronix e.K. | Marc Kleine-Budde |
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