Dear list members,
I'm in the preparation phase of implementing a SocketCAN driver for our CAN-FD capable CAN
interface boards (CAN-PCIe/402 family based on our ESDACC FPGA CAN core).
I've a question regarding on how to implement the bit rate calculation correctly with our
FPGA CAN core. The problem I'm facing is that our CAN core uses only a single prescaler
register "brp" to prepare the input clock for both the arbitration baud rate and the data
baud rate generator.
Looking at the existing code for other CAN-FD capable boards I've seen so far only boards
with two independent "brp" registers. Therefore the values for brp, tseg1, tseg2 and so on
can be calculated independently for the arbitration and the data baud rate and that is what
the code does as far as I understand.
Is there a way to tell the baud rate calculation code that it should use the same brp for
both baud rates?
Can you give me any implementation hints to make it work with the existing baud rate calculation
code?
Best regards,
Stefan Mätje
