On 10.10.2018 13:37, Shubhrajyoti Datta wrote:
> hi ,
Hi!
> On Tue, Sep 11, 2018 at 5:18 PM Anssi Hannula <anssi.hannula@xxxxxxxxxx> wrote:
>> Commit 9e5f1b273e6a ("can: xilinx_can: add support for Xilinx CAN FD
>> core") added a new can_bittiming_const structure for CAN FD cores that
>> support larger values for tseg1, tseg2, and sjw than previous Xilinx CAN
>> cores, but the commit did not actually take that into use.
>>
>> Fix that.
>>
>> Tested with CAN FD core on a ZynqMP board.
>>
>> Fixes: 9e5f1b273e6a ("can: xilinx_can: add support for Xilinx CAN FD core")
>> Reported-by: Shubhrajyoti Datta <shubhrajyoti.datta@xxxxxxxxx>
>> Signed-off-by: Anssi Hannula <anssi.hannula@xxxxxxxxxx>
>> Cc: Michal Simek <michal.simek@xxxxxxxxxx>
>> ---
>> drivers/net/can/xilinx_can.c | 2 +-
>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/drivers/net/can/xilinx_can.c b/drivers/net/can/xilinx_can.c
>> index 045f0845e665..3df23487487f 100644
>> --- a/drivers/net/can/xilinx_can.c
>> +++ b/drivers/net/can/xilinx_can.c
>> @@ -1424,7 +1424,7 @@ static const struct xcan_devtype_data xcan_canfd_data = {
>> XCAN_FLAG_RXMNF |
>> XCAN_FLAG_TX_MAILBOXES |
> sequencial or mailbox is a design choice ?
> What happens if one selects sequencial mode in vivado?
RX sequential/mailbox is a design choice in Vivado, but TX is not
configurable.
>> XCAN_FLAG_RX_FIFO_MULTI,
>> - .bittiming_const = &xcan_bittiming_const,
>> + .bittiming_const = &xcan_bittiming_const_canfd,
>> .btr_ts2_shift = XCAN_BTR_TS2_SHIFT_CANFD,
>> .btr_sjw_shift = XCAN_BTR_SJW_SHIFT_CANFD,
>> .bus_clk_name = "s_axi_aclk",
>> --
>> 2.17.1
>>
--
Anssi Hannula / Bitwise Oy
+358 503803997
