On 7/3/19 2:49 AM, Roman Penyaev wrote:
It seems you took the chunk of the code with macros from
tools/arch/x86/include/asm/barrier.h, where indeed smp_store_release
and smp_load_acquire are defined only for x86-64. If I am not mistaken
kernel defines both __smp_store_release / __smp_load_acquire equally
for x86 memory model in arch/x86/include/asm/barrier.h.
Agreed.
Since there are 32-bit x86 CPUs that can reorder loads and stores
Only "loads may be reordered with earlier stores"
(Intel® 64 and IA-32 Architectures, section 8.2.3.4), but "stores are not
reordered with earlier loads" (section 8.2.3.3), so smp_store_release and
and smp_load_acquire can be relaxed.
Certain IA-32 CPUs do not follow that model. From Linux kernel v4.15:
config X86_PPRO_FENCE
bool "PentiumPro memory ordering errata workaround"
depends on M686 || M586MMX || M586TSC || M586 || M486 || MGEODEGX1
---help---
Old PentiumPro multiprocessor systems had errata that could cause
memory operations to violate the x86 ordering standard in rare cases.
Enabling this option will attempt to work around some (but not all)
occurrences of this problem, at the cost of much heavier spinlock and
memory barrier operations.
If unsure, say n here. Even distro kernels should think twice before
enabling this: there are few systems, and an unlikely bug.
Since support for these CPUs has been removed from the Linux kernel it's
probably fine not to worry about these CPUs in liburing either. See also
commit 5927145efd5d ("x86/cpu: Remove the CONFIG_X86_PPRO_FENCE=y
quirk") # v4.16.
Bart.
