On Wed, Oct 23, 2024 at 04:14:34PM +0800, Ming Lei wrote: > On Wed, Oct 23, 2024 at 08:12:33AM +0200, Christoph Hellwig wrote: > > On Tue, Oct 22, 2024 at 11:24:31AM +0100, Catalin Marinas wrote: > > > > > We should not allow smaller than cache line alignment on architectures > > > > > that are not cache coherent indeed. > > > > > > Even on architectures that are not fully coherent, the coherency is a > > > property of the device. You may need to somehow pass this information in > > > struct queue_limits if you want it to be optimal. > > > > Well, devices set the queue limits. So this would be a fix in the > > drivers that set the queue limits. SCSI already does this in the > > midlayer code, > > I guess it isn't true: > > [linux]# cat /sys/block/sda/queue/dma_alignment Is that a SCSI HBA that is on a not DMA coherent bus? If not that is expected.
