On Wed, Oct 16, 2024 at 10:04:19AM +0200, Christoph Hellwig wrote:
> On Wed, Oct 16, 2024 at 12:40:13AM +0800, Ming Lei wrote:
> > Hello Guys,
> >
> > Turns out host controller's DMA alignment is often too relax, so two DMA
> > buffers may cross same cache line easily, and trigger the warning of
> > "cacheline tracking EEXIST, overlapping mappings aren't supported".
> >
> > The attached test code can trigger the warning immediately with CONFIG_DMA_API_DEBUG
> > enabled when reading from one scsi disk which queue DMA alignment is 3.
> >
>
> We should not allow smaller than cache line alignment on architectures
> that are not cache coherent indeed.
Yes, something like the following change:
diff --git a/block/blk-settings.c b/block/blk-settings.c
index a446654ddee5..26bd0e72c68e 100644
--- a/block/blk-settings.c
+++ b/block/blk-settings.c
@@ -348,7 +348,9 @@ static int blk_validate_limits(struct queue_limits *lim)
*/
if (!lim->dma_alignment)
lim->dma_alignment = SECTOR_SIZE - 1;
- if (WARN_ON_ONCE(lim->dma_alignment > PAGE_SIZE))
+ else if (lim->dma_alignment < L1_CACHE_BYTES - 1)
+ lim->dma_alignment = L1_CACHE_BYTES - 1;
+ else if (WARN_ON_ONCE(lim->dma_alignment > PAGE_SIZE))
return -EINVAL;
if (lim->alignment_offset) {
Thanks,
Ming
