On Wed, Oct 16, 2024 at 04:31:45PM +0800, Ming Lei wrote: > On Wed, Oct 16, 2024 at 10:04:19AM +0200, Christoph Hellwig wrote: > > On Wed, Oct 16, 2024 at 12:40:13AM +0800, Ming Lei wrote: > > > Hello Guys, > > > > > > Turns out host controller's DMA alignment is often too relax, so two DMA > > > buffers may cross same cache line easily, and trigger the warning of > > > "cacheline tracking EEXIST, overlapping mappings aren't supported". > > > > > > The attached test code can trigger the warning immediately with CONFIG_DMA_API_DEBUG > > > enabled when reading from one scsi disk which queue DMA alignment is 3. > > > > > > > We should not allow smaller than cache line alignment on architectures > > that are not cache coherent indeed. > > Yes, something like the following change: We only really need this if the architecture support cache incoherent DMA. Maybe even as a runtime setting.
