On 22-11-21, 11:05, Katherine Perez wrote:
> TLMM controller base address is incorrect and will hang on some platforms.
> Fix by giving the correct address.
Thanks, recheck the spec this looks correct. We should have tlmm reg
space here and not tlmm base which also contains xpu region (thus hang)
Reviewed-by: Vinod Koul <vkoul@xxxxxxxxxx>
Fixes: b7e8f433a673 ("arm64: dts: qcom: Add basic devicetree support for SM8350 SoC")
>
> Signed-off-by: Katherine Perez <kaperez@xxxxxxxxxxxxxxxxxxx>
> ---
> arch/arm64/boot/dts/qcom/sm8350.dtsi | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi
> index d134280e2939..624d294612d8 100644
> --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi
> @@ -960,9 +960,9 @@ spmi_bus: spmi@c440000 {
> #interrupt-cells = <4>;
> };
>
> - tlmm: pinctrl@f100000 {
> + tlmm: pinctrl@f000000 {
> compatible = "qcom,sm8350-tlmm";
> - reg = <0 0x0f100000 0 0x300000>;
> + reg = <0 0x0f000000 0 0x300000>;
> interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
> gpio-controller;
> #gpio-cells = <2>;
> --
> 2.31.1
--
~Vinod
