Quoting Rakesh Pillai (2021-09-16 09:52:01)
> diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dts b/arch/arm64/boot/dts/qcom/sc7280-idp.dts
> index 64fc22a..2b8bbcd 100644
> --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dts
> +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dts
> @@ -1423,6 +1433,59 @@
> #power-domain-cells = <1>;
> };
>
> + remoteproc_wpss: remoteproc@8a00000 {
> + compatible = "qcom,sc7280-wpss-pil";
> + reg = <0 0x08a00000 0 0x10000>;
> +
> + interrupts-extended = <&intc GIC_SPI 587 IRQ_TYPE_EDGE_RISING>,
> + <&wpss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
> + <&wpss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
> + <&wpss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
> + <&wpss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
> + <&wpss_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
> + interrupt-names = "wdog", "fatal", "ready", "handover",
> + "stop-ack", "shutdown-ack";
> +
> + clocks = <&gcc GCC_WPSS_AHB_BDG_MST_CLK>,
> + <&gcc GCC_WPSS_AHB_CLK>,
> + <&gcc GCC_WPSS_RSCP_CLK>,
> + <&rpmhcc RPMH_CXO_CLK>;
> + clock-names = "gcc_wpss_ahb_bdg_mst_clk",
> + "gcc_wpss_ahb_clk",
> + "gcc_wpss_rscp_clk",
> + "xo";
> +
> + power-domains = <&rpmhpd SC7280_CX>,
> + <&rpmhpd SC7280_MX>;
> + power-domain-names = "cx", "mx";
> +
> + memory-region = <&wpss_mem>;
> +
> + qcom,qmp = <&aoss_qmp>;
> +
> + qcom,smem-states = <&wpss_smp2p_out 0>;
> + qcom,smem-state-names = "stop";
> +
> + resets = <&aoss_reset AOSS_CC_WCSS_RESTART>,
> + <&pdc_reset PDC_WPSS_SYNC_RESET>;
> + reset-names = "restart", "pdc_sync";
> +
> + qcom,halt-regs = <&tcsr_mutex_regs 0x37000>;
Where is this node defined? I don't see it on the mailing list for
sc7280. Can you indicate what patches this depends on, and use git
format-patch --base= so we can try to find them ourselves.
