Hi,
On 8/28/2021 9:52 PM, Konrad Dybcio wrote:
+
+ tcsr_mutex: hwlock@1f40000 {
+ compatible = "qcom,tcsr-mutex";
+ reg = <0x0 0x01f40000 0x0 0x40000>;
+ #hwlock-cells = <1>;
+ };
+
+ pdc: interrupt-controller@b220000 {
+ compatible = "qcom,sm6350-pdc", "qcom,pdc";
+ reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x64>;
The second reg 0x17c000f0 is neither documented nor used in PDC irq chip driver. can you please remove it?
Thanks,
Maulik
Wouldn't it make more sense to keep it (like in other PDC-enabled SoCs' device trees) so that there's no
need to add it back when the driver gains support for spi_configure_type (I believe that's what it's used for)?
The second reg in some of the PDC enabled SoCs' went in since it may
have slipped throgh code reviews when using downstream
patch as is on upstream.
Also the bindings document for PDC is still in txt, so yaml check could
not catch the extra register which is not documented.
An attempt to add support for spi_configure_type [1] & [2] had
suggestion either to access second reg via mailbox or
add another level of irqchip hierarchy between PDC to GIC to configure
SPI type. Unless both [1] and [2] patch can go in as
PDC irqchip driver won't gain support to use it. (using mailbox approch
will have mailbox driver to access this register and PDC node may
mention which mailbox to use).
[1]
https://patchwork.kernel.org/project/linux-arm-msm/patch/1568411962-1022-7-git-send-email-ilina@xxxxxxxxxxxxxx/
[2]
https://patchwork.kernel.org/project/linux-arm-msm/patch/1568411962-1022-8-git-send-email-ilina@xxxxxxxxxxxxxx/
Thanks,
Maulik
Konrad
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
