Fixup the register regions used by the cpufreq node on SM8350 SoC to
support per core L3 DCVS.
Signed-off-by: Sibi Sankar <sibis@xxxxxxxxxxxxxx>
---
arch/arm64/boot/dts/qcom/sm8350.dtsi | 9 ++++-----
1 file changed, 4 insertions(+), 5 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi
index a631d58166b1..d0a5a5568602 100644
--- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi
@@ -967,11 +967,10 @@
};
cpufreq_hw: cpufreq@18591000 {
- compatible = "qcom,sm8350-cpufreq-epss", "qcom,cpufreq-epss";
- reg = <0 0x18591000 0 0x1000>,
- <0 0x18592000 0 0x1000>,
- <0 0x18593000 0 0x1000>;
- reg-names = "freq-domain0", "freq-domain1", "freq-domain2";
+ compatible = "qcom,cpufreq-epss";
+ reg = <0 0x18591100 0 0x900>,
+ <0 0x18592100 0 0x900>,
+ <0 0x18593100 0 0x900>;
clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
clock-names = "xo", "alternate";
--
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