Re-arranging the register regions to support per core L3 DCVS would lead to bindings breakage when using an older dt with a newer kernel. So, document the EPSS compatible for SM8250/SM8350 SoCs and use them in the CPUFreq-hw driver to prevent such breakages. Signed-off-by: Sibi Sankar <sibis@xxxxxxxxxxxxxx> --- Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.txt | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.txt b/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.txt index 9299028ee712..ee52fd8d3c9a 100644 --- a/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.txt +++ b/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.txt @@ -8,7 +8,11 @@ Properties: - compatible Usage: required Value type: <string> - Definition: must be "qcom,cpufreq-hw" or "qcom,cpufreq-epss". + Definition: must be one of: + "qcom,cpufreq-epss" + "qcom,cpufreq-hw" + "qcom,sm8250-cpufreq-epss" + "qcom,sm8350-cpufreq-epss" - clocks Usage: required -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project
