Hi Uwe,
On Fri, Jul 16 2021, Uwe Kleine-König wrote:
> On Fri, Jul 16, 2021 at 08:51:20AM +0300, Baruch Siach wrote:
>> On Wed, Jul 14 2021, Uwe Kleine-König wrote:
>> > On Tue, Jul 13, 2021 at 02:35:43PM +0300, Baruch Siach wrote:
>> >> + val = FIELD_PREP(IPQ_PWM_REG0_HI_DURATION, hi_dur) |
>> >> + FIELD_PREP(IPQ_PWM_REG0_PWM_DIV, pwm_div);
>> >> + ipq_pwm_reg_write(pwm, IPQ_PWM_CFG_REG0, val);
>> >> +
>> >> + val = FIELD_PREP(IPQ_PWM_REG1_PRE_DIV, pre_div);
>> >> + ipq_pwm_reg_write(pwm, IPQ_PWM_CFG_REG1, val);
>> >> +
>> >> + /* Enable needs a separate write to REG1 */
>> >> + val |= IPQ_PWM_REG1_UPDATE;
>> >
>> > Setting this bit results in the two writes above being configured
>> > atomically so that no mixed settings happen to the output, right?
>>
>> I guess so. I have no access to hardware documentation, mind you. I
>> first tried to do only one write to REG1, but it had no effect. The
>> existence of the UPDATE bit also indicates that hardware works as you
>> suggest.
>
> I wouldn't trust HW documentation here. If you have some means to
> inspect the waveform this is easy to test. Depending on how long you can
> make the periods an LED is enough. If you start with a slower parent
> clk, a big pre_div and hi_dur = 0 the LED is supposed to be off. Then
> set hi_dur = pwm_div/2 which either make the LED blink slowly or keeps
> off. Then setting pre_div = 2 either increased the blink frequency or it
> doesn't. ...
I currently have only access to DVM to measure the PWM effect. I'll try
to do more measures when I have access to better equipment.
baruch
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