On 2021-07-13 17:05, Baruch Siach wrote:
According to Bjorn Andersson[1], &tcsr_q6 base is 0x01937000 with size
0x21000. Adjust qcom,halt-regs offsets (add 0x8000) to match the new
syscon base.
[1] https://lore.kernel.org/r/YLgO0Aj1d4w9EcPv@yoga
Signed-off-by: Baruch Siach <baruch@xxxxxxxxxx>
---
v5: New patch in this series
---
arch/arm64/boot/dts/qcom/ipq6018.dtsi | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
index 6ee7b99c21ec..72ac36c1be57 100644
--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
@@ -270,9 +270,9 @@ tcsr_mutex_regs: syscon@1905000 {
reg = <0x0 0x01905000 0x0 0x8000>;
};
- tcsr_q6: syscon@1945000 {
+ tcsr_q6: syscon@1937000 {
We can remove the q6 reference and make it as just 'tcsr'?
compatible = "syscon";
- reg = <0x0 0x01945000 0x0 0xe000>;
+ reg = <0x0 0x01937000 0x0 0x21000>;
};
blsp_dma: dma-controller@7884000 {
@@ -615,7 +615,7 @@ q6v5_wcss: remoteproc@cd00000 {
clocks = <&gcc GCC_PRNG_AHB_CLK>;
clock-names = "prng";
- qcom,halt-regs = <&tcsr_q6 0xa000 0xd000 0x0>;
+ qcom,halt-regs = <&tcsr_q6 0x12000 0x15000 0x8000>;
This seems to be not correct. 0x01945000 - 0x01937000 = 0xE000 but here
the values are adjusted with 0x8000 not with 0xE000.
qcom,smem-states = <&wcss_smp2p_out 0>,
<&wcss_smp2p_out 1>;
--
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