Quoting Krishna Manikandan (2021-02-12 02:49:58) > Add YAML schema for the device tree bindings for DSI > > Signed-off-by: Krishna Manikandan <mkrishn@xxxxxxxxxxxxxx> > > Changes in v1: > - Separate dsi controller bindings to a separate patch (Stephen Boyd) > - Merge dsi-common-controller.yaml and dsi-controller-main.yaml to > a single file (Stephen Boyd) > - Drop supply entries and definitions from properties (Stephen Boyd) > - Modify phy-names property for dsi controller (Stephen Boyd) > - Remove boolean from description (Stephen Boyd) > - Drop pinctrl properties as they are standard entries (Stephen Boyd) > - Modify the description for ports property and keep the reference > to the generic binding where this is defined (Stephen Boyd) > - Add description to clock names (Stephen Boyd) > - Correct the indendation (Stephen Boyd) > - Drop the label for display dt nodes and correct the node > name (Stephen Boyd) > > Changes in v2: > - Drop maxItems for clock (Stephen Boyd) > - Drop qcom,mdss-mdp-transfer-time-us as it is not used in upstream > dt file (Stephen Boyd) > - Keep child node directly under soc node (Stephen Boyd) > - Drop qcom,sync-dual-dsi as it is not used in upstream dt > > Changes in v3: > - Add description for register property (Stephen Boyd) > --- > .../bindings/display/msm/dsi-controller-main.yaml | 201 +++++++++++++++++ > .../devicetree/bindings/display/msm/dsi.txt | 249 --------------------- > 2 files changed, 201 insertions(+), 249 deletions(-) > create mode 100644 Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml > delete mode 100644 Documentation/devicetree/bindings/display/msm/dsi.txt > > diff --git a/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml b/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml > new file mode 100644 > index 0000000..2e9269d > --- /dev/null > +++ b/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml > @@ -0,0 +1,201 @@ > +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/display/msm/dsi-controller-main.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Description of Qualcomm Display DSI controller dt properties > + > +maintainers: > + - Krishna Manikandan <mkrishn@xxxxxxxxxxxxxx> > + > +description: | > + Common Device tree bindings for DSI controller. > + > +allOf: > + - $ref: "../dsi-controller.yaml#" > + > +properties: > + compatible: > + items: > + - const: qcom,mdss-dsi-ctrl > + > + reg: > + items: > + - description: Address offset and size for dsi register set > + > + reg-names: > + const: dsi_ctrl > + > + interrupts: > + maxItems: 1 > + > + clocks: > + items: > + - description: Display byte clock > + - description: Display byte interface clock > + - description: Display pixel clock > + - description: Display escape clock > + - description: Display AHB clock > + - description: Display AXI clock > + > + clock-names: > + items: > + - const: byte > + - const: byte_intf > + - const: pixel > + - const: core > + - const: iface > + - const: bus > + > + phys: > + minItems: 1 maxItems:1 ? > + phy-names: > + const: dsi > + > + syscon-sfpb: > + description: A phandle to mmss_sfpb syscon node (only for DSIv2). > + $ref: "/schemas/types.yaml#/definitions/phandle" > + > + qcom,dual-dsi-mode: > + type: boolean > + description: | > + Indicates if the DSI controller is driving a panel which needs > + 2 DSI links. > + > + qcom,master-dsi: > + type: boolean > + description: | > + Indicates if the DSI controller is driving the master link of > + the 2-DSI panel. > + > + ports: > + type: object > + description: | > + Contains DSI controller input and output ports as children, each > + containing one endpoint subnode as defined in > + Documentation/devicetree/bindings/graph.txt and > + Documentation/devicetree/bindings/media/video-interfaces.txt. > + > + properties: > + port@0: > + type: object > + description: | > + Input endpoints of the controller. > + > + properties: > + reg: > + const: 0 > + > + endpoint: > + type: object > + properties: > + remote-endpoint: > + description: | > + For port@0, set to phandle of the connected panel/bridge's > + input endpoint. For port@1, set to the MDP interface output. > + See Documentation/devicetree/bindings/graph.txt for > + device graph info. > + > + data-lanes: > + description: | > + This describes how the physical DSI data lanes are mapped > + to the logical lanes on the given platform. The value contained in > + index n describes what physical lane is mapped to the logical lane n > + (DATAn, where n lies between 0 and 3). The clock lane position is fixed > + and can't be changed. Hence, they aren't a part of the DT bindings. See > + Documentation/devicetree/bindings/media/video-interfaces.txt for > + more info on the data-lanes property. > + > + items: > + - const: 0 > + - const: 1 > + - const: 2 > + - const: 3 Is data-lanes not already covered by some more generic binding? > + port@1: > + type: object > + description: | > + Output endpoints of the controller. > + properties: > + reg: > + const: 1 > + > + endpoint: > + type: object > + properties: > + remote-endpoint: true > + data-lanes: > + items: > + - const: 0 > + - const: 1 > + - const: 2 > + - const: 3 > + > +required: > + - compatible > + - reg > + - reg-names > + - interrupts > + - clocks > + - clock-names > + - phys > + - phy-names > + - ports > + > +unevaluatedProperties: false > + > +examples: > + - | > + #include <dt-bindings/interrupt-controller/arm-gic.h> > + #include <dt-bindings/clock/qcom,dispcc-sdm845.h> > + #include <dt-bindings/clock/qcom,gcc-sdm845.h> > + > + soc { > + #address-cells = <2>; > + #size-cells = <2>; Please remove soc from the example > + > + dsi@ae94000 { > + compatible = "qcom,mdss-dsi-ctrl"; > + reg = <0 0x0ae94000 0 0x400>; > + reg-names = "dsi_ctrl"; > + > + interrupt-parent = <&mdss>; > + interrupts = <4>; > + > + clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, > + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, > + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, > + <&dispcc DISP_CC_MDSS_ESC0_CLK>, > + <&dispcc DISP_CC_MDSS_AHB_CLK>, > + <&dispcc DISP_CC_MDSS_AXI_CLK>; > + clock-names = "byte", > + "byte_intf", > + "pixel", > + "core", > + "iface", > + "bus"; > + > + phys = <&dsi0_phy>; > + phy-names = "dsi"; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@0 { > + reg = <0>; > + dsi0_in: endpoint { > + remote-endpoint = <&dpu_intf1_out>; > + }; > + }; > + > + port@1 { > + reg = <1>; > + dsi0_out: endpoint { > + }; > + }; > + }; > + }; > + }; > +...