Quoting AngeloGioacchino Del Regno (2021-01-14 14:10:59) > The GPU PLL0 is not a fixed PLL and the rate can be set on it: > this is necessary especially on boards which bootloader is setting > a very low rate on this PLL before booting Linux, which would be > unsuitable for postdividing to reach the maximum allowed Adreno GPU > frequency of 710MHz (or, actually, even 670MHz..) on this SoC. > > To allow setting rates on the GPU PLL0, also define VCO boundaries > and set the CLK_SET_RATE_PARENT flag to the GPU PLL0 postdivider. > > With this change, the Adreno GPU is now able to scale through all > the available frequencies. BTW, you're probably undervolting your GPU and clocking it higher than it should be at the voltage from boot. > > Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@xxxxxxxxxxxxxx> > --- > drivers/clk/qcom/gpucc-msm8998.c | 10 +++++++++- > 1 file changed, 9 insertions(+), 1 deletion(-) > > diff --git a/drivers/clk/qcom/gpucc-msm8998.c b/drivers/clk/qcom/gpucc-msm8998.c > index 1a518c4915b4..fedfffaf0a8d 100644 > --- a/drivers/clk/qcom/gpucc-msm8998.c > +++ b/drivers/clk/qcom/gpucc-msm8998.c > @@ -50,6 +50,11 @@ static struct clk_branch gpucc_cxo_clk = { > }, > }; > > +static struct pll_vco fabia_vco[] = { Should be const. > + { 249600000, 2000000000, 0 }, > + { 125000000, 1000000000, 1 }, > +}; > + > static const struct clk_div_table post_div_table_fabia_even[] = { > { 0x0, 1 }, > { 0x1, 2 },