Hello, This series adds APCS mailbox and clock support for SDX55. The APCS IP in SDX55 provides IPC and clock functionalities. Hence, mailbox support is added to the "qcom-apcs-ipc-mailbox" driver and a dedicated clock driver "apcs-sdx55" is added. Also, the clock to the APCS block is coming from 3 different sources: 1. Board XO 2. Fixed rate GPLL0 3. A7 PLL First source is from crystal osc, second is from GCC and third one is a separate clock source. Hence, a dedicated clk driver is added for the A7 PLL as well. Apart from the mailbox support, another intention of this series is to add the CPUFreq support to SDX55 platform. Since there is no dedicated hardware IP in SDX55 to do CPUFreq duties, this platform makes use of the clock and regulators directly via cpufreq-dt driver. The trick here is attaching the power domain to cpudev. Usually the power domains for the target device is attached in the bus driver or in the dedicated device drivers. But in this case, there is no dedicated CPUFreq driver nor a bus driver. After discussing with Viresh, I concluded that A7 PLL driver might be the best place to do this! But this decision is subject to discussion, hence added Ulf and Viresh to this series. Thanks, Mani Manivannan Sadhasivam (5): dt-bindings: mailbox: Add binding for SDX55 APCS mailbox: qcom: Add support for SDX55 APCS IPC dt-bindings: clock: Add Qualcomm A7 PLL binding clk: qcom: Add A7 PLL support clk: qcom: Add SDX55 APCS clock controller support .../devicetree/bindings/clock/qcom,a7pll.yaml | 51 ++++++ .../mailbox/qcom,apcs-kpss-global.yaml | 59 +++++-- drivers/clk/qcom/Kconfig | 17 ++ drivers/clk/qcom/Makefile | 2 + drivers/clk/qcom/a7-pll.c | 100 ++++++++++++ drivers/clk/qcom/apcs-sdx55.c | 149 ++++++++++++++++++ drivers/mailbox/qcom-apcs-ipc-mailbox.c | 5 + 7 files changed, 374 insertions(+), 9 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/qcom,a7pll.yaml create mode 100644 drivers/clk/qcom/a7-pll.c create mode 100644 drivers/clk/qcom/apcs-sdx55.c -- 2.25.1
