Older chipsets may not be allowed to configure certain LLCC registers as that is handled by the secure side software. However, this is not the case for newer chipsets and they must configure these registers according to the contents of the SCT table, while keeping in mind that older targets may not have these capabilities. So add support to allow such configuration of registers to enable capacity based allocation and power collapse retention for capable chipsets. Reason for choosing capacity based allocation rather than the default way based allocation is because capacity based allocation allows more finer grain partition and provides more flexibility in configuration. As for the retention through power collapse, it has an advantage where the cache hits are more when we wake up from power collapse although it does burn more power but the exact power numbers are not known at the moment. Patch 1 is a cleanup to separate out llcc attribute configuration to its own function. Patch 2 adds support for chipsets capable of writing to llcc registers. Changes in v4: * Separate out llcc attribute config to its own function (Stephen) * Pass qcom_llcc_config instead of a new llcc_drvdata property (Doug) Changes in v3: * Drop separate table and use existing qcom_llcc_config (Doug) * More descriptive commit msg (Doug) * Directly set the config instead of '|=' (Doug) Changes in v2: * Fix build errors reported by kernel test robot. Isaac J. Manjarres (1): soc: qcom: llcc: Support chipsets that can write to llcc Sai Prakash Ranjan (1): soc: qcom: llcc: Move attribute config to its own function drivers/soc/qcom/llcc-qcom.c | 100 +++++++++++++++++++++++------------ 1 file changed, 65 insertions(+), 35 deletions(-) base-commit: 75894849c81ab9a2e9df2e8cf2f9c52035cd22a0 -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
